/*
Title:  Top Module
Author: ChinniKrishna Kothapalli
Version: 0.1
Created for: ECE510: System Verilog Final Project
Description: This module integrates the bus activity monitor with UART
*/
module top;
	timeunit 1ns;
	timeprecision 1ns;
	//Variables for UART
	reg Clock,Recieve,Transmit,Error;
	BusInterface Channel();
	BAMToUARTInterface UartBus();
	Bam B1(Channel.BamInputPort,UartBus.BAMToUART);
	CpuStub C1(Channel.CPUPort);
	UARTModule U1(UartBus.UARTToBAM,Clock,Receive,Transmit,Error);

//Uart Clock
initial
  begin
    Clock = 1'b0;        
    forever #62ns Clock = ~Clock; //62ns for getting 8.064 MHz
  end

initial
begin
	assign U1.Recieve = U1.Transmit;     // Put design in loopback mode for testing
end
endmodule
